Phase lock loops (PLLs) are found in a myriad of electronic applications such as communication receivers and clock synchronization circuits for computer systems. A conventional PLL comprises a phase detector for monitoring the phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO) and generating an up control signal and a down control signal for a charge pump circuit which charges and discharges the loop filter at the input of the VCO. The up and down control signals drive the VCO to maintain a predetermined phase relationship between the signals applied to the phase detector, as is well understood.
It is common for the PLL to lose phase lock should the input signal fade or jump to a radically different frequency of operation. The out-of-lock state can be detected with a lock detection circuit and the system processing suspended until the PLL can re-achieve phase lock. Most, if not all, such lock detection schemes monitor the up control signal and the down control signal at the output of the phase detector to ascertain the lock status of the PLL. If the up control signal and down control signal are not pulsing, then loop node voltage remains substantially constant and the PLL should be in phase lock. When the up control signal and the down control signal are steadily generating pulses charging or discharging the loop filter to adjust the input voltage of the VCO, the loop must be in motion and thus out of phase lock.
During normal operation, the loop node is continuously subjected to leakage through the charge pump circuit thus requiring occasional pulses to maintain the voltage controlling the VCO. However, these intermittent pulses should not indicate an out-of-lock condition. The conventional lock detection circuit typically includes a delay circuit comprising, for example, a string of serially coupled inverters designed to ignore short intermittent pulses from the phase detector having less than a predetermined pulse width. The up and down control signals must have a pulse width as least as long as the delay circuit to trigger an out-of-lock signal. Unfortunately, the pulse widths of the up and down control signals are subject to temperature and process variation and therefore are not well suited as control parameters for ascertaining phase lock. The pulse widths of the up and down control signals are merely rough indicators having limited accuracy of the true phase relationship between the input signals of the phase detector.
Hence, what is needed is an improved lock detection circuit for a PLL which directly monitors the input signals of the phase detector to determine the lock status of the loop.